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MPC8308 数据表(PDF) 49 Page - Freescale Semiconductor, Inc |
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MPC8308 数据表(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 88 page  MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 49 Enhanced Secure Digital Host Controller (eSDHC) Figure 34 provides the eSDHC clock input timing diagram. Figure 34. eSDHC Clock Input Timing Diagram 13.2.1 Full-Speed Output Path (Write) Figure 35 provides the data and command output timing diagram. Figure 35. Full-Speed Output Path eSDHC tSFSCKR External Clock VM VM VM tSFSCK tSFSCKF VM = Midpoint Voltage (NVDD/2) operational mode tSFSCKL tSFSCKH Input at the MPC8308 Pins SD CLK at the MPC8308 Pin Output Valid Time: tSFSKHOV Output Hold Time: tSFSKHOX tIH (5 ns) tCLK_DELAY SD CLK at Driving Edge Sampling Edge the Card Pin tISU (5 ns) tDATA_DELAY tSFSCKL tSFSCK (Clock Cycle) Output from the MPC8308 Pins |
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