BFC237018564 datasheet(14/18 Pages) VISHAY

14 / 18 page

MKT 370

Vishay BCcomponents

DC Film Capacitors

MKT Radial Potted Type

www.vishay.com

For technical questions, contact: dc-film@vishay.com

Document Number: 28108

Revision: 04-Aug-09

APPLICATION NOTE AND LIMITING CONDITIONS

These capacitors are not suitable for mains applications as across-the-line capacitors without additional protection, as described

hereunder. These mains applications are strictly regulated in safety standards and therefore electromagnetic interference

suppression capacitors conforming the standards must be used.

To select the capacitor for a certain application, the following conditions must be checked:

1. The peak voltage (UP) shall not be greater than the rated DC voltage (URdc)

2. The peak-to-peak voltage (UP-P) shall not be greater than 2√2 x URac to avoid the ionisation inception level

3. The voltage peak slope (dU/dt) shall not exceed the rated voltage pulse slope in an RC-circuit at rated voltage and without

ringing. If the pulse voltage is lower than the rated DC voltage, the rated voltage pulse slope may be multiplied by URdc and

divided by the applied voltage.

For all other pulses following equation must be fulfilled:

T is the pulse duration.

4. The maximum component surface temperature rise must be lower than the limits (see figure max. allowed component

temperature rise).

5. Since in circuits used at voltages over 280 V peak-to-peak the risk for an intrinsically active flammability after a capacitor

breakdown (short circuit) increases, it is recommended that the power to the component is limited to 100 times the values

mentioned in the table: “Heat conductivity”

6. When using these capacitors as across-the-line capacitor in the input filter for mains applications or as series connected with

an impedance to the mains the applicant must guarantee that the following conditions are fulfilled in any case (spikes and

surge voltages from the mains included).

Voltage Conditions for 6 Above

EXAMPLE

C = 330 nF - 63 V used for the voltage signal shown in next drawing.

UP-P = 40 V; UP = 35 V; T1 = 100 µs; T2 = 200 µs

The ambient temperature is 35 °C

Checking conditions:

1.The peak voltage UP = 35 V is lower than 63 Vdc

2.The peak-to-peak voltage 40 V is lower than 2

√2 x 40 Vac = 113 U

P-P

3.The voltage pulse slope (dU/dt) = 40 V/100 µs = 0.4 V/µs

This is lower than 60 V/µs (see specific reference data for each version)

4.The dissipated power is 16.2 mW as calculated with fourier terms

The temperature rise for Wmax. = 3.5 mm and pitch = 5 mm will be 16.2 mW/3.0 mW/°C = 5.4 °C

This is lower than 15 °C temperature rise at 35 °C, according figure max. allowed component temperature rise

5. Not applicable

6. Not applicable

Voltage Signal

ALLOWED VOLTAGES

Tamb ≤ 85 °C

85 °C < Tamb ≤ 100 °C for 63 V

85 °C < Tamb ≤ 105 °C for > 63 V

Maximum continuous RMS voltage

URac

See “Max. AC voltage as function

of temperature CBB952” per

characteristics

Maximum temperature RMS-overvoltage (< 24 h)

1.25 x URac

URac

Maximum peak voltage (VO-P) (< 2 s)

1.6 x URdc

1.3 x URdc

2 x

-------

⎝⎠

⎛⎞

∫

x dt

Rdc x

-------

⎝⎠

⎛⎞

rated

Voltage

Time

UP-P

BFC237018564 数据表(PDF) 14 Page - Vishay Siliconix

BFC237018564 数据表(HTML) 14 Page - Vishay Siliconix

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

数据表下载