ADT7461A

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13

transmitted over the serial bus in a single read or

write operation is limited only by what the master

and slave devices can handle.

3. When all data bytes have been read or written,

stop conditions are established. In write mode, the

master pulls the data line high during the tenth

clock pulse to assert a stop condition. In read

mode, the master device overrides the

acknowledge bit by pulling the data line high

during the low period before the ninth clock pulse.

This is known as no acknowledge. The master

takes the data line low during the low period

before the tenth clock pulse, then high during the

tenth clock pulse to assert a stop condition.

Any number of bytes of data are transferable over

the serial bus in one operation, but it is not

possible to mix read and write in one operation

because the type of operation is determined at the

beginning and cannot subsequently be changed

without starting a new operation. For the

ADT7461A, write operations contain either one or

two bytes, while read operations contain one byte.

To write data to one of the device data registers, or to read

data from it, the address pointer register must be set so that

the correct data register is addressed. The first byte of a write

operation always contains a valid address that is stored in the

address pointer register. If data is to be written to the device,

the write operation contains a second data byte that is written

to the register selected by the address pointer register.

This procedure is illustrated in Figure 15. The device

address is sent over the bus followed by R/W set to 0. This

is followed by two data bytes. The first data byte is the

address of the internal data register to be written to, which

is stored in the address pointer register. The second data byte

is the data to be written to the internal data register.

Figure 15. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

Figure 16. Writing to the Address Pointer Register Only

Figure 17. Reading from a Previously Selected Register

D7

D6

D5

D4

D3

D2

D1

D0

FRAME 3

DATA BYTE

ACK. BY

ADT7461A

STOP BY

MASTER

SDATA (CONTINUED)

SCLK (CONTINUED)

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK. BY

ADT7461A

SDATA

SCLK

START BY

MASTER

FRAME 2

ADDRESS POINTER REGISTER BYTE

D7

D6

D5

D4

D3

D2

D1

D0

A6

A5

A4

A3

A2

A1

A0

R/W

ACK. BY

ADT7461A

1

1

9

9

1

9

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK. BY

ADT7461A

SDATA

SCLK

START BY

MASTER

FRAME 2

ADDRESS POINTER REGISTER BYTE

D7

D6

D5

D4

D3

D2

D1

D0

A6

A5

A4

A3

A2

A1

A0

R/W

ACK. BY

ADT7461A

1

1

9

9

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK. BY

ADT7461A

SDATA

SCLK

START BY

MASTER

FRAME 2

ADDRESS POINTER REGISTER BYTE

D7

D6

D5

D4

D3

D2

D1

D0

A6

A5

A4

A3

A2

A1

A0

R/W

ACK. BY

ADT7461A

1

1

9

9

STOP BY

MASTER