ADT7467ARQZ-R7 datasheet(69/77 Pages) ONSEMI

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ADT7467

Rev. 3 | Page 69 of 77 | www.onsemi.com

Table 37. Register 0x62—Enhanced Acoustics Register 1 (Power-On Default = 0x00)

Bit

Name

R/W1

Description

<2:0>

ACOU

Read/write

These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping instantaneously to

its newly calculated speed, PWM1 ramps gracefully at the rate determined by these bits. This feature

enhances the acoustics of the fan being driven by the PWM1 output.

Time Slot Increase

Time for 33% to 100%

000 = 1

35 sec

001 = 2

17.6 sec

010 = 3

11.8 sec

011 = 5

7 sec

100 = 8

4.4 sec

101 = 12

3 sec

110 = 24

1.6 sec

111 = 48

0.8 sec

<3>

EN1

Read/write

When this bit is 1, acoustic enhancement is enabled on PWM1 output.

<4>

SYNC

Read/write

SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to

three fans to be driven from PWM3 output and their speeds to be measured.

SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output.

<5>

MIN1

Read/write

When the ADT7467 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or

at PWM1 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value.

0 = 0% duty cycle below TMIN – hysteresis.

1 = PWM1 minimum duty cycle below TMIN – hysteresis.

<6>

MIN2

Read/write

When the ADT7467 is in automatic fan speed control mode and the controlling temperature is below its

TMIN – hysteresis value, this bit defines whether PWM2 is off (0% duty cycle) or at PWM2 minimum duty cycle.

0 = 0% duty cycle below TMIN – hysteresis.

1 = PWM2 minimum duty cycle below TMIN – hysteresis.

<7>

MIN3

Read/write

When the ADT7467 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty

cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value.

0 = 0% duty cycle below TMIN – hysteresis.

1 = PWM3 minimum duty cycle below TMIN – hysteresis.

1 This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.

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