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ADT7481ARMZ-R7 数据表(PDF) 3 Page - ON Semiconductor |
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ADT7481ARMZ-R7 数据表(HTML) 3 Page - ON Semiconductor |
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3 / 20 page ![]() ADT7481 http://onsemi.com 3 PIN ASSIGNMENT Pin No. Mnemonic Description 1 VDD Positive Supply, 3.0 V to 3.6 V. 2 D1+ Positive Connection to the Remote 1 Temperature Sensor. 3 D1− Negative Connection to the Remote 1 Temperature Sensor. 4 THERM Open−Drain Output. Requires pullup resistor. Signals overtemperature events, could be used to turn a fan on/off, or throttle a CPU clock. 5 GND Supply Ground Connection. 6 D2− Negative Connection to the Remote 2 Temperature Sensor. 7 D2+ Positive Connection to the Remote 2 Temperature Sensor. 8 ALERT/THERM2 Open−Drain Logic Output. Used as interrupt or SMBALERT. This may also be configured as a second THERM output. Requires pullup resistor. 9 SDATA Logic Input/Output, SMBus Serial Data. Open−Drain Output. Requires pullup resistor. 10 SCLK Logic Input, SMBus Serial Clock. Requires pullup resistor. TIMING SPECIFICATIONS (Note 1) Parameter Limit at TMIN and TMAX Unit Description fSCLK 400 kHz max tLOW 4.7 ms min Clock low period, between 10% points tHIGH 4.0 ms min Clock high period, between 90% points tR 1.0 ms max Clock/data rise time tF 300 ns max Clock/data fall time tSU; STA 4.7 ms min Start condition setup time tHD; STA (Note 2) 4.0 ms min Start condition hold time tSU; DAT (Note 3) 250 ns min Data setup time tSU; STO (Note 4) 4.0 ms min Stop condition setup time tBUF 4.7 ms min Bus free time between stop and start conditions 1. Guaranteed by design, not production tested. 2. Time from 10% of SDATA to 90% of SCLK. 3. Time for 10% or 90% of SDATA to 10% of SCLK. 4. Time for 90% of SCLK to 10% of SDATA. Figure 2. Serial Bus Timing SCLK SDATA tR tF tLOW tHD;DAT tHD;STA tHIGH tSU;DAT STOP START STOP START tSU;STA tSU;STO tHD;STA tBUF |
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