ADT7486AARMZ-R7 datasheet(4/14 Pages) ONSEMI

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ADT7484A/ADT7486A

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ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, = VCC = VMIN to VMAX, unless otherwise noted)

Parameter

Unit

Max

Typ

Min

Conditions

Temperature-to-Digital Converter

Conversion Time (Local Temperature)

(Note 1)

Averaging enabled

Conversion Time (Remote Temperature)

(Note 1)

Averaging enabled

Total Monitoring Cycle Time (Note 1)

Averaging enabled

Digital Inputs (ADD0, ADD1)

Input High Voltage, VIH

2.3

Input Low Voltage, VIL

0.8

Input High Current, IIH

VIN = VCC

−1.0

Input Low Current, IIL

VIN = 0

1.0

Pin Capacitance

5.0

Digital I/O (SST Pin)

Input High Voltage, VIH

1.1

Input Low Voltage, VIL

0.4

Hysteresis (Note 1)

Between input switching levels

150

Output High Voltage, VOH

ISOURCE = 6 mA (maximum)

1.1

1.9

High Impedance State Leakage, ILEAK

Device powered on SST bus;

VSST = 1.1 V, VCC = 3.3 V

±1.0

High Impedance State Leakage, ILEAK

Device unpowered on SST bus;

VSST = 1.1 V, VCC = 0 V

±10

Signal Noise Immunity, VNOISE

Noise glitches from

10 MHz to 100 MHz; width up to 50 ns

300

p-p

SST Timing

Bitwise Period, tBIT

0.495

500

High Level Time for Logic 1, tH1

(Note 2)

tBIT defined in speed negotiation

0.6 x tBIT

0.75 x tBIT

0.8 x tBIT

High Level Time for Logic 0, tH0

(Note 2)

0.2 x tBIT

0.25 x tBIT

0.4 x tBIT

Time to Assert SST High for Logic 1,

tSU, HIGH

0.2 x tBIT

Hold Time, tHOLD (Note 3)

See SST Specification Rev 1.0

0.5 x tBIT−M

Stop Time, tSTOP

Device responding to a constant low

level driven by originator

1.25 x tBIT

2 x tBIT

Time to Respond After a Reset, tRESET

0.4

Response Time to Speed Negotiation

After Powerup

Time after powerup when device can

participate in speed negotiation

500

1. Guaranteed by design, not production tested.

2. Minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse.

3. Devices compatible with hold time specification as driven by SST originator.

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