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STE100P

7

DEVICE OPERATION

The STE100P integrates the IEEE802.3u compliant functions of PCS (Physical Coding Sub-layer), PMA

(Physical Medium Attachment), and PMD(Physical Medium Dependent) for 100Base-TX, and the

IEEE802.3 compliant functions of Manchester encoding/decoding and transceiver for 10Base-T. All the

functions and operation schemes are described in the following sections.

7.1 100Base-TX Transmit Operation

Regarding the 100Base-TX transmission, the device provides the transmission functions of PCS, PMA,

and PMD for encoding of MII data nibbles to five-bit code-groups (4B/5B), scrambling, serialization of

scrambled code-groups, converting the serial NRZ code into NRZI code, converting the NRZI code into

MLT3 code, and then driving the MLT3 code into the category 5 Unshielded Twisted Pair cable through

an isolation transformer with the turns ratio of 1:1.

Data code-groups Encoder: In normal MII mode application, the device receives nibble type 4B data via

the TxD0~3 inputs of the MII. These inputs are sampled by the device on the rising edge of Tx-clk and

passed to the 4B/5B encoder to generate the 5B code-group used by 100Base-TX.

Idle code-groups: In order to establish and maintain the clock synchronization, the device needs to keep

transmitting signals to the medium. The device will generate Idle code-groups for transmission when there

is no real data want to be sent by MAC.

Start-of-Stream Delimiter-SSD (/J/K/): In a transmission stream, the first 16 nibbles are MAC preamble.

In order to let partner delineate the boundary of a data transmission sequence and to authenticate carrier

events, the device will replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups.

End-of-Stream Delimiter-ESD (/T/R/): In order to indicate the termination of the normal data transmis-

sions, the device will insert 2 nibbles of /T/R/ code-group after the last nibble of FCS.

Scrambling: All the encoded data(including the idle, SSD, and ESD code-groups) is passed to the data

scrambler to reduce the EMI and spread the power spectrum using a 10-bit scrambler seed loaded at the

beginning.

7~3

PAD4:0

PHY Address [4:0]:

The values of the PAD[4:0] pins are latched to this register at

power-up/reset. The first PHY address bit transmitted or

received is the MSB of the address (bit 4). A station

management entity connected to multiple PHY entities must

know the appropriate address of each PHY. A PHY address of

<00000> that is latched in to the part at power-up/reset will

cause the Isolate bit of the PR0 (bit 10, register address 00h)

to be set.

After power up/reset the only way to enable or disable isolate

mode is to set or clear the Isolate bit (bit 10) PR0. After power

up/reset writing <00000> to bits [4:0] of this register will not

cause the part to enter isolate mode.

[00001]

Strap,

R/W

2

---

reserved

0

RO

1

MFPSE

MF Preamble Suppression Enable

1 = Accept management frames with pre-amble suppressed.

0 = Do not accept management frames with preamble

suppressed.

This bit also controls the value of bit 6 in PR1 (MFPS).

1R/W

0

---

reserved

0

RO

Table 5. Register Descriptions (continued)

Bit #

Name

Descriptions

Default Val

RW Type