TSA1002 datasheet(12/20 Pages) STMICROELECTRONICS

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TSA1002 APPLICATION NOTE

DETAILED INFORMATION

The TSA1002 is a high speed analog to digital

converter based on a pipeline architecture and the

latest deep submicron CMOS process to achieve

the best performances in terms of linearity and

power consumption.

The pipeline structure consists of 9 internal

conversion stages in which the analog signal is

fed and sequentially converted into digital data.

Each 8 first stages consists of an Analog to Digital

converter, a Digital to Analog converter, a Sample

and Hold and a gain of 2 amplifier. A 1.5bit

conversion resolution is achieved in each stage.

The latest stage simply is a comparator. Each

resulting LSB-MSB couple is then time shifted to

recover from the conversion delay. Digital data

correction

completes

the

processing

recovering from the redundancy of the (LSB-MSB)

couple for each stage. The corrected data are

outputted through the digital buffers.

Input signal is sampled on the rising edge of the

clock while digital outputs are delivered on the

falling edge of the Data Ready signal.

The advantages of such a converter reside in the

combination of pipeline architecture and the most

advanced technologies. The highest dynamic

performances are achieved while consumption

remains at the lowest level.

Some functionalities have been added in order to

simplify as much as possible the application

board. These operational modes are described in

the following table.

The TSA1002 is pin to pin compatible with the

8bits/40Msps

TSA0801,

the

10bits/25Msps

TSA1001 and the 12bits/50Msps TSA1201. This

ensures a conformity within the product family and

above all, an easy upgrade of the application.

OPERATIONAL MODES DESCRIPTION

Data Format Select (DFSB)

When set to low level (VIL), the digital input DFSB

provides a twoís complement digital output MSB.

This can be of interest when performing some

further signal processing.

When set to high level (VIH), DFSB provides a

standard binary output coding.

Output Enable (OEB)

When set to low level (VIL), all digital outputs

remain active and are in low impedance state.

When set to high level (VIH), all digital outputs

buffers are in high impedance state. This results in

lower consumption while the converter goes on

sampling.

When OEB is set to low level again, the data is

then valid on the output with a very short Ton

delay.

The timing diagram page 4 summarizes this

operating cycle.

Out of Range (OR)

This function is implemented on the output stage

in order to set up an "Out of Range" flag whenever

the digital data is over the full scale range.

Typically, there is a detection of all the data being

at í0í or all the data being at í1í. This ends up with

an output signal OR which is in low level state

(VOL) when the data stay within the range, or in

high level state (VOH) when the data are out of the

range.

Inputs

Outputs

Analog input differential level

DFSB

OEB

Most Significant Bit (MSB)

(VIN-VINB)

RANGE

CLK

-RANGE

(VIN-VINB)

CLK

RANGE>

(VIN-VINB)

>-RANGE

CLK

(VIN-VINB)

RANGE

CLK

Complemented D9

-RANGE

(VIN-VINB)

CLK

Complemented D9

RANGE>

(VIN-VINB)

>-RANGE

CLK

Complemented D9

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