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TSA1002IF 数据表(PDF) 16 Page - STMicroelectronics

部件名 TSA1002IF
功能描述  10-BIT, 50MSPS, 50mW A/D CONVERTER
PDF  20 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

TSA1002IF 数据表(HTML) 16 Page - STMicroelectronics

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Obsolete
Product(s)
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TSA1002
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Power consumption
The internal architecture of the TSA1002 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between IPOL and
the analog Ground pins. The figure 10 sums up
the relevant data.
The TSA1002 will combine highest performances
and lowest consumption at 50Msps when Rpol is
in the range of 12k
Ω to 20kΩ.
At lower sampling frequency, this value of resistor
may be changed and the consumption will
decrease as well.
Figure 10 : Analog Current consumption vs. Fs
According value of Rpol polarization resistance
Linearity, distortion performance towards
Clock Duty Cycle variation
The TSA1002 has an outstanding behaviour
towards clock duty cycle variation and it may be
also reinforced with adjustment of analog current
consumption.
Linearity vs. Duty cycle
Fs=50MSPS; consumption optimized; Fin=1MHz
Distortion vs. Duty cycle
Fs=50MSPS; consumption optimized; Fin=1MHz
Linearity vs. Duty cycle
Fs=50MSPS; Icca=20mA; Fin=10MHz
Distortion vs. Duty cycle
Fs=50MSPS; Icca=20mA; Fin=10MHz
0
10
20
30
40
50
60
25
35
45
55
65
75
Fs (MHz)
0
2
4
6
8
10
12
14
16
18
20
RPOL
ICCA
0
10
20
30
40
50
60
70
80
30
40
50
60
70
Duty Cycle (%)
3
4
5
6
7
8
9
10
SINAD
ENOB
SNR
IccA
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
30
40
50
60
70
Duty Cycle (%)
10
20
30
40
50
60
70
SFDR
THD
IccA
30
35
40
45
50
55
60
65
70
75
80
40
45
50
55
60
Duty Cycle (%)
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
SINAD
ENOB
SNR
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
40
45
50
55
60
Duty Cycle (%)
SFDR
THD



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