M41T94

Description

9/41

Figure 4.

Block diagram

1.

Open drain output

Figure 5.

Hardware hookup

1.

CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.

AI04785

COMPARE

VPFD = 4.4V

VCC

COMPARE

VSO = 2.5V

VBL= 2.5V

BL

COMPARE

Crystal

SPI

INTERFACE

REAL TIME CLOCK

CALENDAR

44 BYTES

USER RAM

RTC w/ALARM

& CALIBRATION

WATCHDOG

SQUARE WAVE

SDO

E

SDI

SCL

RSTIN1

POR

SQW

RST

(1)

WDI

WDF

AF

IRQ/FT/OUT

(1)

VBAT

32KHz

OSCILLATOR

RSTIN2

(2.65V if THS = V

SS

)

AI03686

Master

(ST6, ST7, ST9,

ST10, Others)

SPI Interface with

(CPOL, CPHA)(1) =

('0','0') or ('1','1')

D

Q

C

CS3

CS2

CS1

M41T94

E

XXXXX

CQD

XXXXX

CQD

E

E

CQD