68HC705SP7 datasheet(56/230 Pages) FREESCALE

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Interrupts

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Interrupts

4.8 Programmable Timer Interrupts

The 16-bit programmable timer can generate an interrupt whenever the

following events occur:

•

Input capture

•

Output compare

•

Timer counter overflow

Setting the I bit in the condition code register disables timer interrupts.

The controls for these interrupts are in the timer control register (TCR)

located at $0012 and in the status bits in the timer status register (TSR)

located at $0013.

4.8.1 Input Capture Interrupt

An input capture interrupt occurs if the input capture flag (ICF) becomes

set while the input capture interrupt enable bit (ICIE) is also set. The ICF

flag bit is in the TSR, and the ICIE enable bit is located in the TCR. The

ICF flag bit is cleared by a read of the TSR with the ICF flag bit set, and

then followed by a read of the LSB of the input capture register (ICRL)

or by reset. The ICIE enable bit is unaffected by reset.

4.8.2 Output Compare Interrupt

An output compare interrupt occurs if the output compare flag (OCF)

becomes set while the output compare interrupt enable bit (OCIE) is also

set. The OCF flag bit is in the TSR and the OCIE enable bit is in the TCR.

The OCF flag bit is cleared by a read of the TSR with the OCF flag bit

set, and then followed by an access to the LSB of the output compare

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