68HC705SP7 datasheet(121/230 Pages) FREESCALE

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Analog Subsystem

A/D Conversion Methods

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Analog Subsystem

Table 8-4 gives the range of values of each parameter in the A/D timing

conversion; and Table 8-5 gives some A/D conversion examples for

several bit resolutions.

1. Limited by requirement for CEXT to be less than 2.0 µF.

Table 8-4. A/D Conversion Parameters

Name

Function

Min

Typ

Max

Units

Unknown voltage on channel selection bus

VSS

—VDD –1.5

VCAP Charging voltage on external capacitor

VSS

—VDD –1.5

VMAX Maximum charging voltage on external capacitor

—

VDD –1.5

ICHG

Charging current on external ramping capacitor

VDD = 3 VDC

VDD = 5 VDC

Refer to 15.10 Analog Subsystem

Characteristics (5.0 Vdc) and 15.11 Analog

Subsystem Characteristics (3.0 Vdc)

IDIS

Discharge current on external ramping capacitor

Refer to 15.10 Analog Subsystem

Characteristics (5.0 Vdc) and 15.11 Analog

Subsystem Characteristics (3.0 Vdc)

tCHG

Time to charge external capacitor

(100 kHz < fOSC < 4.0 MHz)

4-bit result

6-bit result

8-bit result

10-bit result

12-bit result

0.032

0.128

0.512

2.048

8.192

0.128

0.512

2.048

8.196

32.768

2.56

10.24

40.96

120(1)

tDIS

Time to discharge external capacitor, CEXT

—

/µF

CEXT Capacitance of external ramping capacitor

0.0001

0.1

2.0

µF

Number of counts for ICHG to charge CEXT to VX

1024

65536

counts

Prescaler into timing function (

÷ P)

Using core timer

Using 16-bit programmable timer

Using software loops

user deﬁned

÷ P

fOSC

Clock source frequency

(excluding any prescaling)

Refer to 15.12 Control Timing (5.0 Vdc)

and 15.13 Control Timing (3.0 Vdc)

Freescale Semiconductor, Inc.

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