68HC705SP7 datasheet(149/230 Pages) FREESCALE

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Core Timer

Core Timer Status and Control Register (CTSCR)

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Core Timer

10.3 Core Timer Status and Control Register (CTSCR)

The read/write core timer status and control register (CTSCR) contains

the interrupt flag bits, interrupt enable bits, interrupt flag bit resets, and

the rate selects for the real time interrupt as shown in Figure 10-2.

CTOF — Core Timer Overflow Flag

This read-only flag becomes set when the first eight stages of the core

timer counter roll over from $FF to $00. The CTOF flag bit generates

a timer overflow interrupt request if CTOFE is also set. The CTOF flag

bit is cleared by writing a logic one to the CTOFR bit. Writing to CTOF

has no effect. Reset clears CTOF.

1 = Overflow in core timer has occurred

0 = No overflow of core timer since CTOF last cleared

RTIF — Real-Time Interrupt Flag

This read-only flag becomes set when the selected real time interrupt

(RTI) output becomes active. RTIF generates a real-time interrupt

request if RTIE is also set. The RTIF enable bit is cleared by writing a

logic one to the RTIFR bit. Writing to RTIF has no effect. Reset clears

RTIF.

1 = Overflow in real-time counter has occurred

0 = No overflow of real-time counter since RTIF last cleared

CTOFE — Core Timer Overflow Interrupt Enable

This read/write bit enables core timer overflow interrupts. Reset

clears CTOFE.

1 = Core timer overflow interrupts enabled

0 = Core timer overflow interrupts disabled

$0008

Bit 7

654321

Bit 0

Read:

CTOF

RTIF

CTOFE

RTIE

RT1

RT0

Write:

CTOFR

RTIFR

Reset:

00000011

= Unimplemented

Figure 10-2. Core Timer Status and Control Register (CTSCR)

Freescale Semiconductor, Inc.

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