68HC705SP7 datasheet(159/230 Pages) FREESCALE

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Programmable Timer

Timer Registers (TMRH and TMRL)

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Programmable Timer

The TMRL latch is a transparent read of the LSB until a read of the

TMRH takes place. A read of the TMRH latches the LSB into the TMRL

location until the TMRL is again read. The latched value remains fixed

even if multiple reads of the TMRH take place before the next read of the

TMRL. Therefore, when reading the MSB of the timer at TMRH, the LSB

of the timer at TMRL must also be read to complete the read sequence.

During power-on reset (POR), the counter is initialized to $FFFC and

begins counting after the oscillator startup delay. Because the counter is

16 bits and preceded by a fixed prescaler, the value in the counter

repeats every 262,144 internal bus clock cycles (524,288 oscillator

cycles).

When the free-running counter rolls over from $FFFF to $0000, the timer

overflow flag bit (TOF) is set in the TSR. When the TOF is set, it can

generate an interrupt if the timer overflow interrupt enable bit (TOIE) is

also set in the TCR. The TOF flag bit can only be reset by reading the

TMRL after reading the TSR.

Other than clearing any possible TOF flags, reading the TMRH and

TMRL in any order or any number of times does not have any effect on

the 16-bit free-running counter.

$0018

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

11111111

$0019

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

11111100

= Unimplemented

Figure 11-3. Programmable Timer Registers (TMRH and TMRL)

Freescale Semiconductor, Inc.

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