MAC7200 datasheet(13/976 Pages) FREESCALE

13 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

xiii

11.11.5.3.2

Block Write Access .............................................................................................186

11.11.5.3.3

Single Read Access .............................................................................................187

11.11.5.3.4

Block Read Access ..............................................................................................187

11.11.5.4

Error Handling .........................................................................................................188

11.11.5.4.1

AHB Read/Write Error ........................................................................................188

11.11.5.4.2

Access Termination .............................................................................................188

11.11.5.4.3

Read/Write Access Error Message ......................................................................188

11.11.5.5

Timing Diagram.......................................................................................................189

11.11.6

System Status ...............................................................................................................189

11.11.6.1

Debug Status Messages ...........................................................................................189

11.12

IEEE 1149.1 State Machine and RD/WR Sequences ......................................................190

11.12.1

JTAG State Machine ....................................................................................................190

11.12.2

JTAG Sequence for Accessing Internal Nexus Registers ............................................191

11.12.3

JTAG Sequence for Read Access of Memory-Mapped Resources .............................191

11.12.4

JTAG Sequence for Write Access of Memory-Mapped Resources.............................191

Chapter 12

Enhanced DMA Controller (eDMA) Module

12.1

Overview of the MAC7200 Implementation ...................................................................193

12.1.1

eDMA Features............................................................................................................193

12.1.2

eDMA Implementation ................................................................................................194

12.1.3

eDMA External Pins....................................................................................................195

12.1.4

eDMA Bus Aborts .......................................................................................................195

12.1.5

eDMA Differences from MAC71xx............................................................................195

12.1.6

eDMA Application Usage ...........................................................................................195

12.1.6.1

Enabling the DMA...................................................................................................195

12.1.6.2

General Operation of the DMA ...............................................................................196

12.1.6.3

Configuring the DMA..............................................................................................196

12.1.6.3.1

Arbitration and System Loading..........................................................................196

12.1.6.3.2

Error Signalling ...................................................................................................197

12.1.6.3.3

DEBUG Mode Behavior .....................................................................................198

12.1.6.3.4

Transfer Control Descriptor (TCD) .....................................................................198

12.1.6.3.5

Channel Completion ............................................................................................198

12.1.6.3.6

Channel Activation Method.................................................................................198

12.1.6.4

Using the DMA........................................................................................................199

12.1.6.5

TCD Memory Initialization .....................................................................................200

12.2

The SPP DMA Controller Module (SPP_DMA2)...........................................................200

12.2.1

Overview......................................................................................................................201

12.2.2

Features........................................................................................................................202

12.2.3

External Signal Description .........................................................................................207

12.2.4

Memory Map/Register Definition ...............................................................................207

12.2.4.1

12.2.4.1.1

DMA Control Register (DMACR) ......................................................................209

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