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M34E02-FMB1TP 数据表(PDF) 10 Page - STMicroelectronics |
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M34E02-FMB1TP 数据表(HTML) 10 Page - STMicroelectronics |
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10 / 34 page ![]() Signal description M34E02, M34E02-F 10/34 Doc ID 10367 Rev 10 Figure 5. I2C bus protocol Table 2. Device select code Chip Enable signals Device type identifier Chip Enable bits RW b7(1) 1. The most significant bit, b7, is sent first. b6 b5 b4 b3 b2 b1 b0 Memory area select code (two arrays)(2) 2. E0, E1 and E2 are compared against the respective external pins on the memory device. E2 E1 E0 1 0 1 0 E2 E1 E0 RW Set write protection (SWP) VSS VSS VHV (3) 3. VHV is defined in Table 13. 01 10 00 1 0 Clear write protection (CWP) VSS VCC VHV (3) 01 1 0 Permanently set write protection (PSWP)(2) E2 E1 E0 E2 E1 E0 0 Read SWP VSS VSS VHV (3) 00 1 1 Read CWP VSS VCC VHV (3) 01 1 1 Read PSWP(2) E2 E1 E0 E2 E1 E0 1 SCL SDA SCL SDA SDA Start condition SDA Input SDA Change AI00792c Stop condition 1 23 7 89 MSB ACK Start condition SCL 1 23 7 89 MSB ACK Stop condition |
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