M41T60

Operation

Doc ID 10396 Rev 13

7/27

2

Operation

The M41T60 clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 8 bytes

contained in the device can then be accessed sequentially in the following order:

1.

Seconds register

2.

Minutes register

3.

Hours register

4.

Day register

5.

Date register

6.

Century/month register

7.

Years register

8.

Calibration register

2.1

2-wire bus characteristics

This bus is intended for communication between different ICs. It consists of two lines: one

bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the

SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

●

Data transfer may be initiated only when the bus is not busy.

●

During data transfer, the data line must remain stable whenever the clock line is high.

Changes in the data line while the clock line is high will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.1.1

Bus not busy

Both data and clock lines remain high.

2.1.2

Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

2.1.3

Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.

2.1.4

Data valid

The state of the data line represents valid data when after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line may be

changed during the low period of the clock signal. There is one clock pulse per bit of data.