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P912XDP512F0MPVR 数据表(PDF) 339 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 339 Page - Freescale Semiconductor, Inc |
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339 / 1348 page  Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 339 7.3.2.21 ICPAR — Input Control Pulse Accumulators Register (ICPAR) Read: Anytime Write: Anytime. All bits reset to zero. The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN is set, PA3EN and PA2EN have no effect. The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN is set, PA1EN and PA0EN have no effect. 76543210 R 0000 PA3EN PA2EN PA1EN PA0EN W Reset 00000000 = Unimplemented or Reserved Figure 7-43. Input Control Pulse Accumulators Register (ICPAR) Table 7-25. ICPAR Field Descriptions Field Description 3:0 PA[3:0]EN 8-Bit Pulse Accumulator ‘x’ Enable 0 8-Bit Pulse Accumulator is disabled. 1 8-Bit Pulse Accumulator is enabled. |
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