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P912XDP512F0MPVR 数据表(PDF) 347 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 347 Page - Freescale Semiconductor, Inc |
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347 / 1348 page  Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 347 7.3.2.29 8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H) Read: Anytime. Write: Has no effect. All bits reset to zero. These registers are used to latch the value of the corresponding pulse accumulator when the related bits in register ICPAR are enabled (see Section 7.4.1.3, “Pulse Accumulators”). 76543210 R PA3H7 PA3H6 PA3H5 PA3H4 PA3H3 PA3H2 PA3H1 PA3H0 W Reset 00000000 = Unimplemented or Reserved Figure 7-51. 8-Bit Pulse Accumulators Holding Register 3 (PA3H) 76543210 R PA2H7 PA2H6 PA2H5 PA2H4 PA2H3 PA2H2 PA2H1 PA2H0 W Reset 00000000 = Unimplemented or Reserved Figure 7-52. 8-Bit Pulse Accumulators Holding Register 2 (PA2H) 76543210 R PA1H7 PA1H6 PA1H5 PA1H4 PA1H3 PA1H2 PA1H1 PA1H0 W Reset 00000000 = Unimplemented or Reserved Figure 7-53. 8-Bit Pulse Accumulators Holding Register 1 (PA1H) 76543210 R PA0H7 PA0H6 PA0H5 PA0H4 PA0H3 PA0H2 PA0H1 PA0H0 W Reset 00000000 = Unimplemented or Reserved Figure 7-54. 8-Bit Pulse Accumulators Holding Register 0 (PA0H) |
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