P912XDP512F0MPVR datasheet(372/1348 Pages) FREESCALE

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

372

Freescale Semiconductor

NOTE

PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock

pre-scale is changed while a PWM signal is being generated, a truncated or

stretched pulse can occur during the transition.

8.3.2.5

PWM Center Align Enable Register (PWMCAE)

The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned

outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be

center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See

Section 8.4.2.5, “Left Aligned Outputs” and Section 8.4.2.6, “Center Aligned Outputs” for a more detailed

description of the PWM output modes.

Table 8-4. PWMPRCLK Field Descriptions

Field

Description

6–4

PCKB[2:0]

Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channels 2, 3, 6, or

7. These three bits determine the rate of clock B, as shown in Table 8-5.

2–0

PCKA[2:0]

Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channels 0, 1, 4 or

5. These three bits determine the rate of clock A, as shown in Table 8-6.

Table 8-5. Clock B Prescaler Selects

PCKB2

PCKB1

PCKB0

Value of Clock B

Bus clock

Bus clock / 2

Bus clock / 4

Bus clock / 8

Bus clock / 16

Bus clock / 32

Bus clock / 64

Bus clock / 128

Table 8-6. Clock A Prescaler Selects

PCKA2

PCKA1

PCKA0

Value of Clock A

Bus clock

Bus clock / 2

Bus clock / 4

Bus clock / 8

Bus clock / 16

Bus clock / 32

Bus clock / 64

Bus clock / 128

76543210

CAE7

CAE6

CAE5

CAE4

CAE3

CAE2

CAE1

CAE0

Reset

00000000

Figure 8-7. PWM Center Align Enable Register (PWMCAE)

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