P912XDP512F0MPVR datasheet(401/1348 Pages) FREESCALE

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

401

The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in

Table 9-5. The equation used to generate the SDA Hold value from the IBFD bits is:

SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}

The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:

SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]

SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]

Table 9-5. IIC Divider and Hold Values (Sheet 1 of 5)

IBC[7:0]

(hex)

SCL Divider

(clocks)

SDA Hold

(clocks)

SCL Hold

(start)

SCL Hold

(stop)

MUL=1

104

128

112

128

144

160

192

240

118

121

160

192

224

110

113

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