P912XDP512F0MPVR datasheet(483/1348 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

483

11.3.2.2

SCI Control Register 1 (SCICR1)

Read: Anytime, if AMAP = 0.

Write: Anytime, if AMAP = 0.

NOTE

This register is only visible in the memory map if AMAP = 0 (reset

condition).

Table 11-2. IRSCI Transmit Pulse Width

TNP[1:0]

Narrow Pulse Width

1/4

1/32

1/16

3/16

76543210

LOOPS

SCISWAI

RSRC

WAKE

ILT

Reset

00000000

Figure 11-5. SCI Control Register 1 (SCICR1)

Table 11-3. SCICR1 Field Descriptions

Field

Description

LOOPS

Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI

and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must

be enabled to use the loop function.

0 Normal operation enabled

1 Loop operation enabled

The receiver input is determined by the RSRC bit.

SCISWAI

SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.

0 SCI enabled in wait mode

1 SCI disabled in wait mode

RSRC

Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register

input. See Table 11-4.

0 Receiver input internally connected to transmitter output

1 Receiver input connected externally to transmitter

Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.

0 One start bit, eight data bits, one stop bit

1 One start bit, nine data bits, one stop bit

WAKE

Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the

most signiﬁcant bit position of a received data character or an idle condition on the RXD pin.

0 Idle line wakeup

1 Address mark wakeup

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