P912XDP512F0MPVR datasheet(502/1348 Pages) FREESCALE

502 / 1348 page

Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

502

Freescale Semiconductor

11.4.6

Receiver

Figure 11-20. SCI Receiver Block Diagram

11.4.6.1

Receiver Character Length

The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI

control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in

SCI data register high (SCIDRH) is the ninth bit (bit 8).

11.4.6.2

Character Reception

During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register

is the read-only buffer between the internal data bus and the receive shift register.

After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the

SCI data register. The receive data register full ﬂag, RDRF, in SCI status register 1 (SCISR1) becomes set,

WAKE

ILT

876543210L

11-Bit Receive Shift Register

Data

Wakeup

Parity

Checking

SCI Data Register

ILIE

RWU

RDRF

Internal Bus

Bus

SBR12:SBR0

Baud Divider

Clock

IDLE

RAF

Recovery

Logic

RXPOL

LOOPS

Loop

RSRC

Control

SCRXD

From TXD Pin

or Transmitter

Idle IRQ

RDRF/OR

IRQ

Break

Detect Logic

Active Edge

Detect Logic

BRKDFE

BRKDIE

BRKDIF

RXEDGIE

RXEDGIF

Break IRQ

RX Active Edge IRQ

RIE

P912XDP512F0MPVR 数据表(PDF) 502 Page - Freescale Semiconductor, Inc

P912XDP512F0MPVR 数据表(HTML) 502 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载