P912XDP512F0MPVR datasheet(526/1348 Pages) FREESCALE

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Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

526

Freescale Semiconductor

12.3.2.5

SPI Data Register (SPIDR)

Read: Anytime; normally read only when SPIF is set

Write: Anytime

The SPI data register is both the input and output register for SPI data. A write to this register

allows a data byte to be queued and transmitted. For an SPI conﬁgured as a master, a queued data

byte is transmitted immediately after the previous transmission has completed. The SPI transmitter

empty ﬂag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new

data.

Received data in the SPIDR is valid when SPIF is set.

If SPIF is cleared and a byte has been received, the received byte is transferred from the receive

shift register to the SPIDR and SPIF is set.

If SPIF is set and not serviced, and a second byte has been received, the second received byte is

kept as valid byte in the receive shift register until the start of another transmission. The byte in the

SPIDR does not change.

If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced before the start of

a third transmission, the byte in the receive shift register is transferred into the SPIDR and SPIF

remains set (see Figure 12-8).

If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced after the start of

a third transmission, the byte in the receive shift register has become invalid and is not transferred

into the SPIDR (see Figure 12-9).

76543210

Bit 7

Bit 0

Reset

00000000

Figure 12-7. SPI Data Register (SPIDR)

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