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P912XDP512F0MPVR 数据表(PDF) 549 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 549 Page - Freescale Semiconductor, Inc |
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549 / 1348 page  Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 549 13.3.0.8 PIT Load Register 0 to 3 (PITLD0–3) Read: Anytime Write: Anytime 15 14 13 12 11 10 9876543210 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 000000 0000000000 Figure 13-11. PIT Load Register 0 (PITLD0) 15 14 13 12 11 10 9876543210 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 000000 0000000000 Figure 13-12. PIT Load Register 1 (PITLD1) 15 14 13 12 11 10 9876543210 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 000000 0000000000 Figure 13-13. PIT Load Register 2 (PITLD2) 15 14 13 12 11 10 9876543210 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 000000 0000000000 Figure 13-14. PIT Load Register 3 (PITLD3) Table 13-8. PITLD0–3 Field Descriptions Field Description 15:0 PLD[15:0] PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer has counted down to zero the PTF time-out flag will be set and the register value will be loaded. The PFLT bits in the PITFLT register can be used to immediately update the count register with the new value if an immediate load is desired. |
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