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P912XDP512F0MPVR 数据表(PDF) 601 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 601 Page - Freescale Semiconductor, Inc |
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601 / 1348 page  Chapter 16 Interrupt (S12XINTV1) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 601 16.3.1.1 Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime Address: 0x0121 76543210 R IVB_ADDR[7:0] W Reset 11111111 Figure 16-3. Interrupt Vector Base Register (IVBR) Table 16-2. IVBR Field Descriptions Field Description 7–0 IVB_ADDR[7:0] Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to HCS12. Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset vectors (0xFFFA–0xFFFE). Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”. |
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