P912XDP512F0MPVR datasheet(611/1348 Pages) FREESCALE

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Chapter 16 Interrupt (S12XINTV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

611

Figure 16-14. Interrupt Processing Example

16.5.3

Wake Up from Stop or Wait Mode

16.5.3.1

CPU Wake Up from Stop or Wait Mode

Every I bit maskable interrupt request which is conﬁgured to be handled by the CPU is capable of waking

the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualiﬁed to wake

up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:

•

If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.

•

An I bit maskable interrupt is ignored if it is conﬁgured to a priority level below or equal to the

current IPL in CCR.

•

I bit maskable interrupt requests which are conﬁgured to be handled by the XGATE are not capable

of waking up the CPU.

An XIRQ request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set.

16.5.3.2

XGATE Wake Up from Stop or Wait Mode

Interrupt request channels which are conﬁgured to be handled by the XGATE are capable of waking up the

XGATE. Interrupt request channels handled by the XGATE do not affect the state of the CPU.

Reset

L1 (Pending)

L3 (Pending)

RTI

Stacked IPL

Processing Levels

IPL in CCR

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