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P912XDP512F0MPVR 数据表(PDF) 682 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 682 Page - Freescale Semiconductor, Inc |
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682 / 1348 page  Chapter 18 Memory Mapping Control (S12XMMCV3) MC9S12XDP512 Data Sheet, Rev. 2.21 682 Freescale Semiconductor 18.4.4 Chip Bus Control The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDMand XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping operations. All internal and external resources are connected to specific target buses (see Figure 18-261). Figure 18-26. MMC Block Diagram 1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities. CPU BDM MMC “Crossbar Switch” XGATE S12X1 S12X0 XGATE XBUS3 XBUS0 XBUS1 XRAM XBUS2 DBG FLEXRAY S12X2 IPBI FLASH EETX EBI XSRAM BDM FTX resources |
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