P912XDP512F0MPVR datasheet(699/1348 Pages) FREESCALE

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Chapter 19 S12X Debug (S12XDBGV2) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

701

19.3.1.3

Debug Trace Control Register (DBGTCR)

Read: Anytime

Write: Bits 7:6 only when DBG is neither secure nor armed.

Bits 5:0 anytime the module is disarmed.

0x0022

76543210

TSOURCE

TRANGE

TRCMOD

TALIGN

Reset

00000000

Figure 19-5. Debug Trace Control Register (DBGTCR)

Table 19-8. DBGTCR Field Descriptions

Field

Description

7–6

TSOURCE

Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session. If the MCU

system is secured, these bits cannot be set and tracing is inhibited. See Table 19-9.

5–4

TRANGE[5:4]

Trace Range Bits —The TRANGE bits allow ﬁltering of trace information from a selected address range when

tracing from the CPU in detail mode. The XGATE tracing range cannot be narrowed using these bits. To use a

comparator for range ﬁltering, the corresponding COMPE and SRC bits must remain cleared. If the COMPE bit

is not clear then the comparator will also be used to generate state sequence triggers or tags. If the SRC bit is

set the comparator is mapped to the XGATE busses, corrupting the trace. See Table 19-10.

3–2

TRCMOD[3:2]

Trace Mode Bits — See Section 19.4.5.2, “Trace Modes“ for detailed trace mode descriptions. In normal

mode, change of ﬂow information is stored. In loop1 mode, change of ﬂow information is stored but redundant

entries into trace memory are inhibited. In detail mode, address and data for all memory and register accesses

is stored. See Table 19-11

1–0

TALIGN[1:0]

Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a

tracing session. See Table 19-12.

Table 19-9. TSOURCE Trace Source Bit Encoding

TSOURCE

Tracing Source

No tracing requested

CPU

101

1 No range limitations are allowed. Thus tracing operates as if TRANGE = 00.

XGATE

111, 2

2 No detail mode tracing supported. If TRCMOD =10, no information is stored.

Both CPU and XGATE

Table 19-10. TRANGE Trace Range Encoding

TRANGE

Tracing Source

Trace from all addresses (No ﬁlter)

Trace only in address range from 0x0000 to comparator D

Trace only in address range from comparator C to 0x7FFFFF

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