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P912XDP512F0MPVR 数据表(PDF) 867 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 867 Page - Freescale Semiconductor, Inc |
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867 / 1348 page ![]() Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 869 22.3.2.55 Port J Input Register (PTIJ) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This can be used to detect overload or short circuit conditions on output pins. 76543210 R PTIJ7 PTIJ6 PTIJ5 PTIJ4 0 PTIJ2 PTIJ1 PTIJ0 W Reset1 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. 00000000 = Unimplemented or Reserved Figure 22-57. Port J Input Register (PTIJ) |
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