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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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P912XDP512F0MPVR 数据表(PDF) 875 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 875 Page - Freescale Semiconductor, Inc |
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875 / 1348 page  Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 877 22.3.2.68 Port AD1 Data Direction Register 0 (DDR0AD1) Read: Anytime. Write: Anytime. This register configures pin PAD[23:16] as either input or output. 76543210 R DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116 W Reset 00000000 Figure 22-70. Port AD1 Data Direction Register 0 (DDR0AD1) Table 22-61. DDR0AD1 Field Descriptions Field Description 7–0 DDR0AD1[23:16] Data Direction Port AD1 Register 0 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTAD10 register, when changing the DDR0AD1 register. Note: To use the digital input function on Port AD1 the ATD1 digital input enable register (ATD1DIEN0) has to be set to logic level “1”. |
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