P912XDP512F0MPVR datasheet(885/1348 Pages) FREESCALE

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

887

22.4.3

Pin Interrupts

Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or

falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same

interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.

An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt

enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or

WAIT mode.

A digital filter on each pin prevents pulses (Figure 22-78) shorter than a specified time from generating an

interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 22-77 and

Table 22-69).

Figure 22-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)

Figure 22-78. Pulse Illustration

Table 22-69. Pulse Detection Criteria

Pulse

Mode

STOP

Unit

STOP1

1 These values include the spread of the oscillator frequency over temperature,

voltage and process.

Ignored

tpulse ≤ 3

Bus clocks

tpulse ≤ tpign

Uncertain

3 < tpulse < 4

Bus clocks

tpign < tpulse < tpval

Valid

tpulse ≥ 4

Bus clocks

tpulse ≥ tpval

Glitch, ﬁltered out, no interrupt ﬂag set

Valid pulse, interrupt ﬂag set

tpign

tpval

uncertain

tpulse

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