P912XDP512F0MPVR datasheet(141/1348 Pages) FREESCALE

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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

141

3:0

C[D:A}

Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are

sampled and converted to digital codes. Table 4-17 lists the coding used to select the various analog input

channels.

In the case of single channel conversions (MULT = 0), this selection code speciﬁed the channel to be examined.

In the case of multiple channel conversions (MULT = 1), this selection code represents the ﬁrst channel to be

examined in the conversion sequence. Subsequent channels are determined by incrementing the channel

selection code or wrapping around to AN0 (after converting the channel deﬁned by the Wrap Around Channel

Select Bits WRAP[3:0] in ATDCTL0). In case starting with a channel number higher than the one deﬁned by

WRAP[3:0] the ﬁrst wrap around will be AN15 to AN0.

Table 4-15. Available Result Data Formats.

SRES8

DJM

DSGN

Result Data Formats

Description and Bus Bit Mapping

8-bit / left justiﬁed / unsigned — bits 15:8

8-bit / left justiﬁed / signed — bits 15:8

8-bit / right justiﬁed / unsigned — bits 7:0

10-bit / left justiﬁed / unsigned — bits 15:6

10-bit / left justiﬁed / signed -— bits 15:6

10-bit / right justiﬁed / unsigned — bits 9:0

Table 4-16. Left Justiﬁed, Signed and Unsigned ATD Output Codes.

Input Signal

VRL = 0 Volts

VRH = 5.12 Volts

Signed

8-Bit Codes

Unsigned

8-Bit Codes

Signed

10-Bit Codes

Unsigned

10-Bit Codes

5.120 Volts

5.100

5.080

2.580

2.560

2.540

0.020

0.000

7FC0

7F00

7E00

0100

0000

FF00

8100

8000

FFC0

FF00

FE00

8100

8000

7F00

0100

0000

Table 4-14. ATDCTL5 Field Descriptions (continued)

Field

Description

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