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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

173

5.3.2.6

ATD Control Register 5 (ATDCTL5)

This register selects the type of conversion sequence and the analog input channels sampled. Writes to this

Read: Anytime

Write: Anytime

76543210

DJM

DSGN

SCAN

MULT

Reset

00000000

= Unimplemented or Reserved

Figure 5-8. ATD Control Register 5 (ATDCTL5)

Table 5-13. ATDCTL5 Field Descriptions

Field

Description

DJM

Result Register Data Justiﬁcation — This bit controls justiﬁcation of conversion data in the result registers.

See Section 5.3.2.13, “ATD Conversion Result Registers (ATDDRx),” for details.

0 Left justiﬁed data in the result registers

1 Right justiﬁed data in the result registers

DSGN

Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned

conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed

data is not available in right justiﬁcation. See Section 5.3.2.13, “ATD Conversion Result Registers (ATDDRx),”

for details.

0 Unsigned data representation in the result registers

1 Signed data representation in the result registers

Table 5-14 summarizes the result data formats available and how they are set up using the control bits.

Table 5-15 illustrates the difference between the signed and unsigned, left justiﬁed output codes for an input

signal range between 0 and 5.12 Volts.

SCAN

Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed

continuously or only once.

0 Single conversion sequence

1 Continuous conversion sequences (scan mode)

MULT

Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the speciﬁed

analog input channel for an entire conversion sequence. The analog channel is selected by channel selection

code (control bits CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples

across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C,

S2C, S1C). The ﬁrst analog channel examined is determined by channel selection code (CC, CB, CA control

bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection

code.

0 Sample only one channel

1 Sample across several channels

2–0

CC, CB, CA

Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are

sampled and converted to digital codes. Table 5-16 lists the coding used to select the various analog input

channels. In the case of single channel scans (MULT = 0), this selection code speciﬁed the channel examined.

In the case of multi-channel scans (MULT = 1), this selection code represents the ﬁrst channel to be examined

in the conversion sequence. Subsequent channels are determined by incrementing channel selection code;

selection codes that reach the maximum value wrap around to the minimum value.

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