STM6522

Description

Doc ID 17045 Rev 2

5/25

1

Description

The Smart Reset™ devices provide a useful feature that ensures that inadvertent short

reset push-button closures do not cause system resets as the extended Smart Reset™

delay setup periods are implemented. Once the valid Smart Reset™ input levels and setup

The typical application hookup shows that either a single Smart Reset™ input, or both reset

inputs can be connected to the applications interrupt and control both the interrupt pin and

the hard reset functions. If the push-button is closed for a short time, the processor is only

interrupted. If the system still does not respond properly, holding the push-button(s) for the

feature helps significantly increase system stability and eliminates the need for a dedicated

reset button.

The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset

circuits targeted at applications such as MP3 players, portable navigation or mobile phones,

generally any application that requires delayed reset push-button(s) response for improved

system stability. The devices in the STM65xx Smart Reset™ family include various

combinations of useful features for the targeted applications.

The STM6522 has two combined Smart Reset™ inputs (SR0 and SR1) with delayed reset

Figure 1.

Logic diagram

AM04867v2

VCC

SR0

RST1

RST2

VSS

STM6522

SR1

SRC