ADS58C48IPFPR datasheet(20/70 Pages) TI

20 / 70 page

ADS58C48

SLAS689 – MAY 2010

www.ti.com

ADDRS

DEFAULT

A7-A0 IN

VALUE

HEX

AFTER

RESET

<DATA FORMAT CH C

CH D>

D4-D3

Both channels in 2s complement

Both channels in offset binary

ADDRS

DEFAULT

A7-A0 IN

VALUE

HEX

AFTER

RESET

D7-D4

<GAIN> Gain programmability in 0.5 dB steps for channels A,B,C,D

0000

0 dB gain, default after reset

0001

0.5 dB gain

0010

1.0 dB gain

0011

1.5 dB gain

0100

2.0 dB gain

0101

2.5 dB gain

0110

3.0 dB gain

0111

3.5 dB gain

1000

4.0 dB gain

1001

4.5 dB gain

1010

5.0 dB gain

1011

5.5 dB gain

1100

6 dB gain

D2-D0

<TEST PATTERNS – CH X> Test Patterns to verify data capture for channels A, B, C, D

ONLY when register bit DIGITAL MODE1 is set

000

Normal operation

001

Outputs all zeros

010

Outputs all ones

011

Outputs toggle pattern

Output data <D10:D0> is an alternating sequence of 10101010101 and 01010101010.

100

Outputs digital pattern

Output data increments by one LSB (11-bit) every 8th clock cycle from code 0 to code 2047

101

Outputs custom pattern

(use registers 0x3F, 0x40 for setting the custom pattern)

110

Unused

111

Unused

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