1–10

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Configuration Handbook (Complete Two-Volume Set)

© December 2009

Altera Corporation

Multiple FPGAs can be configured using a single enhanced configuration device in

FPP mode. In this mode, multiple Stratix series FPGAs, APEX II FPGAs, or both, are

cascaded together in a daisy chain.

After the first FPGA completes configuration, its nCEO pin asserts to activate the nCE

pin for the second FPGA, which prompts the second device to start capturing

configuration data. In this setup, the FPGAs CONF_DONE pins are tied together, and

hence all devices initialize and enter user mode simultaneously. If the enhanced

configuration device or one of the FPGAs detects an error, configuration stops (and

simultaneously restarts) for the whole chain because the nSTATUS pins are tied

together.

configuration devices cannot be cascaded to configure larger devices or chains.

Figure 1–2. FPP Configuration

Notes to Figure 1–2:

(2) The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. This means an

external pull-up resistor is not required on the nINIT_CONF / nCONFIG line. The nINIT_CONF pin does not need to be connected if its

(3) The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external

internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.

(4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 1–10.

(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to

F-A16

C-RP#

(6) Connect the FPGA MSEL[] input pins to select the FPP configuration mode. For details, refer to the appropriate FPGA family chapter in the

Configuration Handbook.

Device Protection” on page 1–15.

Enhanced Configuration

Device

DCLK

DATA[7..0]

OE

nCS

nINIT_CONF (2)

MSEL

DCLK

DATA[7..0]

nSTATUS

CONF_DONE

nCONFIG

GND

GND

(3)

(3)

nCE

EXCLK

Stratix Series

or

APEX II Device

WE#C

RP#C

WP#

PORSEL

PGM[2..0]

TMO

WE#F

RP#F

A[20..0]

RY/BY#

CE#

OE#

DQ[15..0]

N.C.

N.C.

N.C.

N.C.

N.C.

BYTE# (5)

TM1

(3)

(3)

C-A0 (5)

C-A1 (5)

C-A15 (5)

C-A16 (5)

A0-F

A1-F

A15-F

A16-F

(1)

(1)

n

(6)

(1)

nCEO

N.C.

(4)

(4)

(4)

VCCW