ISO7421 datasheet(2/20 Pages) TI

2 / 20 page

ISO7420, ISO7420M

ISO7421, ISO7421M

SLLS984D – JUNE 2009 – REVISED JULY 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

NO.

INA

Input, channel A

INB

Input, channel B

GND1

–

Ground connection for VCC1

GND2

–

Ground connection for VCC2

OUTA

Output, channel A

OUTB

Output, channel B

VCC1

–

Power supply, VCC1

VCC2

–

Power supply, VCC2

Table 1. FUNCTION TABLE(1)

INPUT SIDE

OUTPUT SIDE

INPUT

OUTPUT

VCC

OUT

Open

H(2)

(1)

PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.4 V);

X = Irrelevant; H = High level; L = Low level

(2)

In fail-safe condition, output is at high level for ISO7420, ISO7420M,

ISO7421 and ISO7421M.

AVAILABLE OPTIONS

RATED

INPUT

CHANNEL

MARKED

ORDERING

PRODUCT

PACKAGE

RATED TA

ISOLATION

THRESHOLD

DIRECTION

NUMBER

ISO7420D (rail)

ISO7420

–40°C to 105°C

IS7420

ISO7420DR (reel)

Same direction

ISO7420MD (rail)

ISO7420M

–40°C to 125°C

I7420M

ISO7420MDR

(reel)

~1.5 V (TTL)

2.5 kVrms

D-8

(CMOS compatible)

ISO7421D (rail)

ISO7421

–40°C to 105°C

IS7421

ISO7421DR (reel)

Opposite

ISO7421MD (rail)

directions

ISO7421M

–40°C to 125°C

I7421M

ISO7421MDR

(PREVIEW)

(reel)

Submit Documentation Feedback

Product Folder Link(s): ISO7420 ISO7420M ISO7421 ISO7421M

ISO7421 数据表(PDF) 2 Page - Texas Instruments

ISO7421 数据表(HTML) 2 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载