CDCM61002

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SCAS870D – FEBRUARY 2009 – REVISED JULY 2010

Prescaler Divider and Feedback Divider

The VCO output is routed to the prescaler divider and then to the feedback divider. The prescaler divider and

feedback divider are set in tandem with each other, according to the control pin settings given in Table 4. The

allowable combinations of the two dividers ensure that the VCO frequency and the PFD frequency are within the

specified limits.

On-Chip VCO

The CDCM61002 includes an on-chip, LC oscillator-based VCO with low phase noise covering a frequency

range of 1.75 GHz to 2.05 GHz. The VCO must be calibrated to ensure proper operation over the valid device

operating conditions. VCO calibration is controlled by a divided-down reference clock input. This calibration

requires that the PLL be set up properly to lock the PLL loop and that the reference clock input be present.

During the first device initialization after power-up, which occurs after the Power On Reset is released (2.64 V or

lower, over valid device operating conditions) or a device reset with the RSTN pin, a VCO calibration sequence is

initiated after 16384 × Reference Input Clock Cycles. The VCO calibration then takes about 20 ms over the

allowable range of the reference clock input.

The VCO calibration can also be reinitiated with a pulse on the RSTN pin at any time after POR is released on

power-up; the RSTN pulse must be at least 100 ns wide.

Output Divider

The output from the prescaler divider is also routed to the output divider. The output divider can be set with

control pins according to Table 5.

Output Buffer

Each output buffer can be set to LVPECL or LVDS or 2x LVCMOS, according to Table 6. OSC_OUT is an

LVCMOS output that can be used in test mode to monitor proper loading of the input crystal in order to achieve

the necessary crystal frequency with the least error. The output buffers are disabled during VCO calibration and

are enabled only after calibration is complete.

The output buffers on the CDCM61002 can also be disabled, along with other sections of the device, using the

CE pin according to Table 7.

LVCMOS INPUT INTERFACE

Alternately, the CDCM61002 can be operated with an external ac-coupled 2.5-V LVCMOS or dc-coupled 3.3-V

LVCMOS reference input applied to the XIN pin. For optimal jitter performance, a 2.5-V LVCMOS input is

recommended. For proper operation, the LVCMOS reference should be available and fairly stable by the time the

power supply voltages or the RSTN pin voltage on the CDCM61002 reaches 2.27 V. Refer to application report

SCAA111, available for download at ti.com, for more details about the LVCMOS input interface to the

CDCM61002.

Copyright © 2009–2010, Texas Instruments Incorporated

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Product Folder Link(s): CDCM61002