DELAY TIME

TIMING DIAGRAMS

TMP122-EP

The Delay Bits control the amount of time delay between each conversion. This feature allows the user to

maximize power savings by eliminating unnecessary conversions, and minimizing current consumption. During

active conversion the TMP122 typically requires 50

µA of current for approximately 0.25s conversion time, and

approximately 20

µA for idle times between conversions. Delay settings are identified in Table 12 as conversion

time and period, and are shown in Figure 9. Default power up is D1/D0 equal 0/0. Conversion time and

conversion periods scale with resolution. Conversion period denotes time between conversion starts.

Table 12. Conversion Delay for 12-Bit Resolution

D1

D2

CONVERSION TIME

CONVERSION PERIOD

0

0

0.25 s

0.25 s

0

1

0.25 s

0.5 s

1

0

0.25 s

1 s

1

1

0.25 s

8 s

Figure 9. Conversion Time and Period Description

The TMP122 is SPI compatible. Figure 10 to Figure 12 describe the various timing parameters of the TMP122

with timing definitions in Table 13.

Table 13. Timing Description

PARAMETER

MIN

MAX

UNIT

SCK period

100

ns

Data in to rising edge SCK setup time

20

ns

SCK falling edge to output data delay

30

ns

SCK rising edge to input data hold time

20

ns

CS to rising edge SCK set-up time

40

ns

CS to output data delay

30

ns

CS rising edge to output high impedance

30

ns

Copyright © 2008, Texas Instruments Incorporated

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