TMX320C6748ZCE3 datasheet(2/254 Pages) TI

2 / 254 page

TMS320C6748 Fixed/Floating-Point DSP

SPRS590A – JUNE 2009 – REVISED AUGUST 2009

www.ti.com

Unit (PRU) Cores

–

Two 8-bit SD (BT.656), Single 16-bit Video

Display Channels

• 32-Bit Load/Store RISC architecture

• Universal Parallel Port (uPP):

• 4K Byte instruction RAM per core

–

High-Speed Parallel Interface to FPGAs and

• 512 Bytes data RAM per core

Data Converters

• PRU Subsystem (PRUSS) can be

–

Data Width on Each of Two Channels is 8-

disabled via software to save power

to 16-bit Inclusive

• Register 30 of each PRU is exported

–

Single Data Rate or Dual Data Rate

from the subsystem in addition to the

Transfers

normal R31 output of the PRU cores.

–

Supports Multiple Interfaces with START,

–

Standard power management mechanism

ENABLE and WAIT Controls

• Clock gating

• Serial ATA (SATA) Controller:

• Entire subsystem under a single PSC

clock gating domain

–

Supports SATA I (1.5 Gbps) and SATA II

(3.0 Gbps)

–

Dedicated interrupt controller

–

Supports all SATA Power Management

–

Dedicated switched central resource

Features

• USB 1.1 OHCI (Host) With Integrated PHY

–

Hardware-Assisted Native Command

(USB1)

Queueing (NCQ) for up to 32 Entries

• USB 2.0 OTG Port With Integrated PHY (USB0)

–

Supports Port Multiplier and

–

USB 2.0 High-/Full-Speed Client

Command-Based Switching

–

USB 2.0 High-/Full-/Low-Speed Host

• Real-Time Clock With 32 KHz Oscillator and

–

End Point 0 (Control)

Separate Power Rail

–

End Points 1,2,3,4 (Control, Bulk, Interrupt

• Three 64-Bit General-Purpose Timers

or ISOC) Rx and Tx

(Configurable as Two 32-Bit Timers)

• One Multichannel Audio Serial Port:

• One 64-Bit General-Purpose Timer (Watch

–

Transmit/Receive Clocks up to 50 MHz

Dog)

–

Two Clock Zones and 16 Serial Data Pins

• Two Enhanced Pulse Width Modulators

–

Supports TDM, I2S, and Similar Formats

(eHRPWM):

–

DIT-Capable

–

Dedicated 16-Bit Time-Base Counter With

–

FIFO buffers for Transmit and Receive

Period And Frequency Control

• Two Multichannel Buffered Serial Ports:

–

6 Single Edge, 6 Dual Edge Symmetric or 3

–

Transmit/Receive Clocks up to 50 MHz

Dual Edge Asymmetric Outputs

–

Two Clock Zones and 16 Serial Data Pins

–

Dead-Band Generation

–

Supports TDM, I2S, and Similar Formats

–

PWM Chopping by High-Frequency Carrier

–

AC97 Audio Codec Interface

–

Trip Zone Input

–

Telecom Interfaces (ST-Bus, H100)

• Three 32-Bit Enhanced Capture Modules

–

128-channel TDM

(eCAP):

–

FIFO buffers for Transmit and Receive

–

Configurable as 3 Capture Inputs or 3

• 10/100 Mb/s Ethernet MAC (EMAC):

Auxiliary Pulse Width Modulator (APWM)

outputs

–

IEEE 802.3 Compliant

–

Single Shot Capture of up to Four Event

–

MII Media Independent Interface

Time-Stamps

–

RMII Reduced Media Independent Interface

• 361-Ball Pb-Free Plastic Ball Grid Array

–

Management Data I/O (MDIO) Module

(PBGA) [ZCE Suffix], 0.65-mm Ball Pitch

• Video Port Interface (VPIF):

• 361-Ball Pb-Free Plastic Ball Grid Array

–

Two 8-bit SD (BT.656), Single 16-bit or

(PBGA) [ZWT Suffix], 0.80-mm Ball Pitch

Single Raw (8-/10-/12-bit) Video Capture

Channels

• Commercial or Extended Temperature

TMS320C6748 Fixed/Floating-Point DSP

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