SC183CEVB datasheet(18/20 Pages) SEMTECH

18 / 20 page

SC183C

www.semtech.com

Applications Information (continued)

PCB Layout Considerations

The layout diagrams in Figure 5 and Figure 6 show a rec-

ommended PCB layout for a standard V

OUT option and an

adjustable V

OUT option, respectively. Fundamental layout

rules must be followed since the layout is critical for

achieving the performance specified in the Electrical

Characteristics table. Poor layout can degrade the perfor-

mance of the DC-DC converter and can contribute to EMI

problems, ground bounce, and resistive voltage losses.

Poor regulation and instability can result.

The following guidelines are recommended when devel-

oping a PCB layout:

The input capacitor, C

IN, provides a low impedance

loop for the pulsed currents present at the buck

converter’s inputs. C

IN should therefore be placed as

close to the PVIN and PGND pins as possible, and no

more than 3mm away from the PVIN pin. Place the C

and SC183C on the same component side to eliminate

the use of vias between C

IN and the device pins. Use

short wide traces or a copper plane to connect as

closely to the IC as possible. Use multiple vias for the

ground connection to the ground plane to reduce the

parasitic inductance. These measures will minimize

EMI and input voltage ripple by localizing the high

frequency current pulses.

Keep the LX pin traces as short as possible to minimize

pickup of high frequency switching edges to other

parts of the circuit. C

OUT and L should be connected as

close as possible between the LX and GND pins, with

a direct return to the GND pin from C

OUT.

Route the output voltage feedback/sense path away

from the inductor and LX node to minimize noise and

magnetic interference.

Use a ground plane referenced to the SC183C PGND

pin. Use several vias to connect to the component

side ground to further reduce noise and interference

on sensitive circuit nodes.

If possible, minimize the resistance from the VOUT

and AGND pins to the load. This will reduce the

voltage drop on the ground plane and improve the

load regulation. And it will also improve the overall

efficiency by reducing the copper losses on the output

and ground planes.

Figure 5 — Recommended PCB Top & Bottom Layer

Layout for Standard V

OUT Option

(a) Top layer for standard volatge option

(b) Bottom layer for standard voltage option

Figure 6 — Recommended PCB Top & Bottom Layer

Layout for Adjustable V

OUT Option

(a) Top layer for adjustable voltage option

(b) Bottom layer for adjustable voltage option

VIN

GND

VOUT

CTLx

COUT

GND

VIN

VOUT

VIN

GND

VOUT

CTLx

CIN

COUT

GND

VIN

VOUT

RFB1

RFB2

CFF

SC183CEVB 数据表(PDF) 18 Page - Semtech Corporation

SC183CEVB 数据表(HTML) 18 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载

链接网址

SC183CEVB 数据表(PDF) 18 Page - Semtech Corporation

SC183CEVB 数据表(HTML) 18 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表 下载

链接网址

数据表下载