Preliminary
2-199
RF2186
Rev A2 010515
2
Pin
Function
Description
Interface Schematic
1GND1
Ground for first stage. For best performance, keep traces physically
short and connect immediately to ground plane. This ground should be
isolated from the backside ground contact.
See pin 16.
2
VPD1
Power Down control for first and second stages. When this pin is “low”,
all first and second stage circuits are shut off. When this pin is 2.8V, all
first and second stage circuits operate normally. VPD1 requires a regu-
lated 2.8V for the amplifier to operate properly over all specified tem-
perature and voltage ranges. A dropping resistor from a higher
regulated voltage may be used to provide the required 2.8V.
3VMODE
VMODE adjusts the bias to the second and third stages. In normal oper-
ation and for maximum efficiency, VMODE should be “high”. In this mode
the power and linearity will meet the published specifications. If addi-
tional linearity is desired, VMODE may be pulled “low”, however effi-
ciency will decrease. If VMODE is pulled “low”, the output match will
need to be adjusted for optimum performance.
4
VPD2
Power Down control for third stage. When this pin is “low”, all third
stage circuits are shut off. When this pin is 2.8V, all third stage circuits
operate normally. VPD requires a regulated 2.8V for the amplifier to
operate properly over all specified temperature and voltage ranges. A
dropping resistor from a higher regulated voltage may be used to pro-
vide the required 2.8V. A 15pF high frequency bypass capacitor is rec-
ommended.
5BIAS GND
For best performance, keep traces physically short and connect to
ground plane through a 15nH inductor. This ground should be isolated
from the backside ground contact.
6NC
Not Connected.
7RF OUT
RF output and power supply for final stage. This is the unmatched col-
lector output of the third stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 1920MHz to 1980MHz.
It is important to select an inductor with very low DC resistance with a
1A current rating. Alternatively, shunt microstrip techniques are also
applicable and provide very low DC resistance. Low frequency bypass-
ing is required for stability.
8RF OUT
Same as pin 7.
See pin 7.
92FO
Second harmonic trap. Keep traces physically short and connect imme-
diately to ground plane. This ground should be isolated from backside
ground contact.
10
VCC
Supply for bias reference and control circuits. High frequency bypass-
ing may be necessary.
11
VCC2
Power supply for second stage and interstage match. Pins 11 and 12
should be connected by a common trace where the pins contact the
printed circuit board.
12
VCC2
Same as pin 11.
13
NC
Not Connected.
14
NC
Not Connected.
15
VCC1
Power supply for first stage and interstage match. VCC should be fed
through a 1.2nH inductor terminated with a 8.2pF capacitor on the sup-
ply side. The inductor should be as close to the pin as possible.
See pin 16.
16
RF IN
RF input. An external series capacitor is required as a DC block.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered
to a top side ground pad which is connected to the ground plane with
multiple vias. The pad should have a short thermal path to the ground
plane.
RF OUT
From Bias
Network
GND1
RF IN
VCC1
From Bias
Network
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