SC412AEVB datasheet(16/22 Pages) SEMTECH

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SC412A

POWER MANAGEMENT

Layout Guidelines

One or more ground planes are recommended to minimize

the effect of switching noise and copper losses and to

maximize heat removal. The analog ground reference, RTN,

should connect directly to the thermal pad, which in turn

connects to the ground plane through preferably one large

via. There should be a RTN plane or copper are near the

chip; all components that are referenced to RTN should

connect to this plane directly, not through the ground plane,

and located on the chip side of the PCB if possible.

GND should be a separate plane which is not used for

routing analog traces. The VCC input provides power to

the internal analog circuits and the upper and lower gate

drivers.

The VCC supply decoupling capacitor should be tied be-

tween VCC and GND with short traces. All power GND

connections should connect directly to this plane with

special attention given to avoiding indirect connections

between RTN and GND which will create ground loops. As

mentioned above, the RTN plane must be connected to the

GND plane at the chip near the RTN/GND pins.

The switcher power section should connect directly to the

ground plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed to minimize loops

and reduce losses. Make all the power connections on

one side of the PCB using wide copper ﬁlled areas if

possible. Do not use “minimum” land patterns for power

components. Minimize trace lengths and maximize trace

widths between the gate drivers and the gates of the

MOSFETs to reduce parasitic impedances (and MOSFET

switching losses); the low-side MOSFET is most critical.

Maintain a length to width ratio of <20:1 for gate drive

signals. Use multiple vias as required by current handling

requirement (and to reduce parasitic) if routed on more

than one layer.

For an accurate ILIM current sense connection, connect

the ILIM trace to the current sense element (MOSFET or

resistor) directly at the pin of the element, and route that

trace over to the ILIM resistor on another layer if needed.

The layout can be generally considered in two parts; the

control section referenced to RTN, and the switcher power

section referenced to GND.

Looking at the control section ﬁrst, locate all components

referenced to RTN on the schematic and place these

components near the chip and on the same side if possible.

Connect RTN using a wide trace. Very little current ﬂows

in the RTN path and therefore large areas of copper are

not needed. Connect the RTN pin directly to the thermal

pad under the device as the only connection between RTN

and GND.

The chip supply decoupling capacitor (VCC/GND) should

be located near to the pins. Since the DL pin is directly

between VCC and GND, and the DL trace must be a wide,

direct trace, the VCC decoupling capacitor is best placed

on the opposite side of the PCB, routed with traces as short

as possible and using at least two vias when connecting

through the PCB.

There are two sensitive, feedback-related pins at the chip:

VOUT and FB. Proper routing is needed to keep noise

away from these signals. All components connected to

FB should be located directly at the chip, and the copper

area of the FB node minimized. The VOUT trace that

feeds into the VOUT pin, which also feeds the FB resistor

divider, must be kept far away from noise sources such

as switching nodes, inductors and gate drives. Route the

VOUT trace in a quiet layer if possible, from the output

capacitor back to the chip.

For the switcher power section, there are a few key

guidelines to follow:

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