SC417_09 datasheet(21/30 Pages) SEMTECH

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SC417/SC427

Switch-over Limitations on VOUT and VLDO

Because the internal switch-over circuit always compares

the VOUT and VLDO pins at start-up, there are limitations

on permissible combinations of these pins. Consider the

case where V

OUT

is programmed to 3.0V and V

LDO

is pro-

grammed to 3.3V. After start-up, the device would connect

VOUT to VLDO and disable the LDO, since the two volt-

ages are within the ±300mV switch-over window. To avoid

unwanted switch-over, the minimum difference between

the voltages for V

OUT

and V

LDO

should be ±500mV.

It is not recommended to use the switch-over feature for

an output voltage less than 3V since this does not provide

sufficient voltage for the gate-source drive to the internal

p-channel switch-over MOSFET.

Switch-over MOSFET Parasitic Diodes

The switch-over MOSFET contains parasitic diodes that

are inherent to its construction, as shown in Figure 11.

Switchover

MOSFET

Parasitic diode

V5V

VLDO

VOUT

Switchover

control

Figure 11— Switch-over MOSFET Parasitic Diodes

There are some important design rules that must be fol-

lowed to prevent forward bias of these diodes. The fol-

lowing two conditions need to be satisfied in order for the

parasitic diodes to stay off.

V5V ≥ V

LDO

V5V ≥ V

OUT

If either V

LDO

or V

OUT

is higher than V5V, then the respective

diode will turn on and the SC417/SC427 operating current

will flow through this diode. This has the potential of

damaging the device.

•

ENL pin and VIN UVLO

The ENL pin also acts as the switcher under-voltage

lockout for the V

supply. The V

UVLO voltage is pro-

grammable via a resistor divider at the VIN, ENL and AGND

pins.

ENL is the enable/disable signal for the LDO. In order to

implement the VIN UVLO there is also a timing require-

ment that needs to be satisfied.

If the ENL pin transitions low within 2 switching cycles and

is < 1V, then the LDO will turn off but the switcher remains

on. If ENL goes below the VIN UVLO threshold and stays

above 1V, then the switcher will turn off but the LDO

remains on.

The VIN UVLO function has a typical threshold of 2.6V on

the VIN rising edge. The falling edge threshold is 2.4V.

Note that it is possible to operate the switcher with the

LDO disabled, but the ENL pin must be below the logic

low threshold (0.4V maximum).

ENL Logic Control of PWM Operation

When the ENL input is driven above 2.6V, it is impossible

to determine if the LDO output is going to be used to

power the device or not. In self-powered operation where

the LDO will power the device, it is necessary during the

LDO start-up to hold the PWM switching off until the LDO

has reached 90% of the final value. This prevents over-

loading the current-limited LDO output during the LDO

start-up. However, if the switcher was previously operat-

ing (with EN/PSV high but ENL at ground, and V5V sup-

plied externally), then it is undesirable to shut down the

switcher.

To prevent this, when the ENL input is taken above 2.6V

(above the VIN UVLO threshold), the internal logic checks

the PGOOD signal. If PGOOD is high, then the switcher is

already running and the LDO will run through the start-up

cycle without affecting the switcher. If PGOOD is low, then

the LDO will not allow any PWM switching until the LDO

output has reached 90% of it’s final value.

Applications Information (continued)

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