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74ALVT16601DL 数据表(PDF) 7 Page - NXP Semiconductors |
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74ALVT16601DL 数据表(HTML) 7 Page - NXP Semiconductors |
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7 / 20 page ![]() 74ALVT16601_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 5 July 2005 7 of 20 Philips Semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 7. Functional description 7.1 Function table [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition [2] Output level before the indicated steady-state input conditions were established. [3] Output level before the indicated steady-state input conditions were established, provided that CPAB or CPBA was LOW before LEAB or LEBA went LOW. 8. Limiting values VCC 50 voltage supply B2 51 data input or output (B side) B1 52 data input or output (B side) GND 53 ground (0 V) B0 54 data input or output (B side) CPAB 55 A-to-B clock input (active rising edge) CEAB 56 A-to-B clock enable (active LOW) Table 3: Pin description …continued Symbol Pin Description Table 4: Function table [1] Control Input Output CEAB OEAB LEAB CPAB An Bn CEBA OEBA LEBA CPBA Bn An XH XXX Z XL H X L L HH LLL ↑ LL HH LLLH X Y [2] LX Y [3] H LLX X Y [2] Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +4.6 V VI input voltage [1] −0.5 +7.0 V VO output voltage output in OFF-state or HIGH-state [1] −0.5 +7.0 V |
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