CDCE906 datasheet(13/42 Pages) TI

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Block Read Programming Sequence

SCLK

SDATA

Bit 7 (MSB)

Bit 6

Bit 0 (LSB)

th(SDATA)

tsu(SDATA)

tsu(START)

t(BUS)

th(START)

tr(SM)

tf(SM)

tW(SCLH)

tW(SCLL)

tsu(STOP)

VIH(SM)

VIL(SM)

VIH(SM)

VIL(SM)

SMBus Hardware Interface

SDATA

SCLK

SMB Host

CDCE906

CBUS

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

Slave Address

CommandCode

Slave Address

Byte Count N

Data Byte 0

- - - - -

Data Byte N–1

Figure 10. Block Read Protocol

Figure 11. Timing Diagram Serial Control Interface

The following diagram shows how the CDCE906 clock synthesizer is connected to the SMBus. Note that the

current through the pullup resistors (Rp) must meet the SMBus specifications (min 100 µA, max 350 µA). If the

CDCE906 is not connected to the SMBus, then SDATA and SCLK inputs have to be connected with 10-k

Ω

pullup resistors to VCC to avoid floating input conditions.

Figure 12. SMBus Hardware Interface

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