SC453TSTRT datasheet(13/26 Pages) SEMTECH

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POWER MANAGEMENT

SC453

DAC Slew Control

The output of the DAC will slew at a rate defined by the

current in the SS pin and the capacitor applied externally

to the SS pin. The slew rate (charge current) applied de-

pends on which mode (soft-start, VID or sleep transition)

is in effect. A 1nF capacitor is recommended for the DAC

pin.

Blanking During VID Changes

On any VID change or Sleep change, the PG# and PG_

DEL signals are blanked for 62 switching cycles to prevent

glitching during the transition.

Sleep Function and SLPV/VID Sleep Mode

By default, the controller is in SLPV controlled sleep mode.

In this mode, the voltage applied to the SLPV pin appears

at the DAC output when SLP is asserted high. This mode

is selected by connecting the SLPV to a resistor divider

from the HYS pin,

VID sleep mode is selected by connecting the SLPV pin to

VCCA during startup. In this mode, the DAC output contin-

ues to be set by the VID inputs even when SLP is asserted

high.

During sleep mode, the hysteresis current used for PWM

switching and for current limit are reduced to 70% of their

nominal values.

CORE CONVERTER CONTROLLER

Core Comparator

This is an ultra-fast hysteretic comparator with a typical

propagation delay of 20ns for 20mV overdrive. Hysteresis

is generated by the current set at the HYS pin impressed

upon an external resistor connected to the CMP pin.

Current Limit Comparator

The Current Limit Comparator compares the voltage be-

tween the CL and CLREF pins. The CL pin monitors the

inductor current using the voltage drop across a resistor

connected in series with the inductor. The CLREF voltage

determines the upper limit for the Current Limit Compara-

tor. The upper limit is equal to the (3 x HYS) current multi-

plied by the resistance connected to the CLREF pin.

A current limit condition occurs when the CL voltage ex-

ceeds the CLREF voltage, at which point the high side

FETs are turned off. The high side FETs will not be en-

abled again until the inductor current drops below the

lower current limit threshold. The upper and lower current

limit thresholds are programmed by the voltage drop im-

pressed upon an external resistor connected to the CLRF

pin. The voltage drop is equal to the HYS current multi-

plied by the

Current Limit Latch

If the CORE voltage goes lower than 14% below the VID

(i.e., out of the power good window), then sustained cur-

rent limiting (32 current limit pulses) will cause the part

to permanently latch off. The latch is inhibited during soft-

start.

Core Converter Soft-Start Timer

This block controls the start-up ramp time of the CORE

voltage up to the boot voltage. The primary purpose is to

reduce the initial in-rush current on the core input voltage

(battery) rail.

Cycle-by-Cycle Power-Save

A zero crossing comparator detects when the currents

through the external sense resistor reduces to zero. When

the current in the external sense resistor reaches zero,

the bottom FET is latched off. The latch is reset when the

controller decides to switch on the top FET. This prevents

excessive switching at light loads and hence saves switch-

ing power losses.

Applications Information (Cont.)

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