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11-95
RF2908
Rev C1 010904
11
Detailed Functional Block Diagram
LNA
+45°
-45°
0-25 dB
0-20 dB
-12-+12
17dB
6dB
-0.5/-20.5
Chip
Control
PLL ON
RX ENABL
BW SEL2
BW SEL1
RSSI Q
RSSI I
VREF
LNA IN
SW GND1
SW GND2
LNA GND
MIX VCC
MOUT I+
MOUT I-
IN I+
IN I-
GND1
GND2
GND3
DCFB I
DCFB Q
IF OUT Q
Q DATA
IF OUT I
I DATA
5-bit Counter
/32
Prescaler
32/33
7-Bit Swallow
Counter
0-85
7-Bit
Latch
Phase
Detector
Charge Pump
7-Bit Counter
/94
902-928
MHz
VCO
Ref. Osc.
300 kHz
300 kHz
OSC B
OSC E
DO
46
14
13
12
11
3
35
36
37
38
1
2
48 47
44
4
6
8
10
7
9
5
43
17
20
39
42
45
22
41
40
21
19
15
18
16
7
30 31
32 33
29
28
23
24
7-Bit Shift
Register
PLL CLK
LE
PLL DATA
7
26
25
27
34
VGC