Preliminary
5-93
RF9678
Rev A4 010622
5
Pin
Function
Description
Interface Schematic
1VGC
Analog gain control for AGC amplifiers. Valid control voltage ranges are
from 0.2VDC to 2.4VDC. The gain range for the AGC is 55dB. These
voltages are valid ONLY for a 39k
Ω source impedance. A DC voltage
less than or equal to the maximum allowable VCC may be applied to
this pin when no voltage is applied to the VCC pins.
2VCC2
DC supply. This pin should be bypassed to ground with a 10nF capaci-
tor.
3MOD+
Same as pin 4, except complementary output.
See pin 4.
4MOD-
One half of the balanced AGC output port. The impedance of this port
is 200
Ω balanced. This pin requires an inductor to V
CC to achieve full
dynamic range. In order to maximize gain, this inductor should be a
high-Q type and should be parallel resonated out with a capacitor (see
application schematic). This pin is NOT DC blocked. A blocking capaci-
tor of 2200pF is needed when this pin is connected to a DC path. An
appropriate matching network may be needed if an IF filter is used.
5
I SIG+
One half of the balanced baseband input to the I mixer. This pin is DC-
coupled and must be supplied with 1.3VDC to bias the input transistor.
Input impedance of this pin is 10k
Ω minimum. For maximum carrier
suppression, DC voltage on this pin relative to ISIG- DC voltage may be
adjusted. (In case a balun is needed, a seperate balun board (RD0102
PCBA) could be ordered as an accessory.)
See pin 8.
6
I SIG-
One half of the balanced baseband input to the I mixer. This pin is DC-
coupled and must be supplied with 1.3VDC to bias the input transistor.
Input impedance of this pin is 10k
Ω minimum. For maximum carrier
suppression, DC voltage on this pin relative to ISIG+ DC voltage may
be adjusted.
7
Q SIG+
One half of the balanced baseband input to the Q mixer. This pin is DC-
coupled and must be supplied with 1.3VDC to bias the input transistor.
Input impedance of this pin is 10k
Ω minimum. For maximum carrier
suppression, DC voltage on this pin relative to QSIG- DC voltage may
be adjusted.
See pin 10.
8
Q SIG-
One half of the balanced baseband input to the Q mixer. This pin is DC-
coupled and must be supplied with 1.3VDC to bias the input transistor.
Input impedance of this pin is 10k
Ω minimum. For maximum carrier
suppression, DC voltage on this pin relative to QSIG+ DC voltage may
be adjusted.
9LO-
One half of the balanced modulator LO1 input. In single-ended applica-
tions (100
Ω input impedance), this pin is AC grounded with a 1nF
capacitor.
See pin 10.
10
LO+
One half of the balanced modulator LO1 input. The other half of the
input, LO1-, is AC grounded for single-ended input applications. The
frequency on these pins is divided by a factor of 2, hence the carrier
frequency for the modulator becomes one half of the applied frequency.
The single-ended input impedance is 1k
Ω (balanced is 2kΩ). This pin
is NOT internally DC blocked. An external blocking capacitor (1nF rec-
ommended) must be provided if the pin is connected to a device with
DC present.
11
BG OUT
Bandgap voltage reference. This voltage, constant over temperature
and supply variation, is used to bias internal circuits. A 10nF external
bypass capacitor is required.
12
NC
No connection.
13
VCC1
DC supply. This pin should be bypassed to ground with a 10nF capaci-
tor.
14
AGC DEC
AGC decoupling pin. An external bypass capacitor of 10nF capacitor is
required. The trace length between the pin and the bypass capacitors
should be minimized. The ground side of the bypass capacitors should
connect immediately to ground plane.
VGC
BIAS
BIAS
BIAS
MOD OUT-
MOD OUT+
I SIG-
I SIG+
Q SIG-
Q SIG+
LO1+,
FM+
LO1-,
FM-
BIAS
BIAS
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